#22 (Apr 22, 2020, 6:16:55 PM)

Started by remote host 89.156.65.194 with note: null

• origin/riscv

1. check-typo (commit: 05d4d20) (details / githubweb)
2. Changes (commit: 4c74fea) (details / githubweb)
3. Review (commit: 8e558d9) (details / githubweb)
4. Review (commit: a2d1f59) (details / githubweb)
5. Add NOTES.md (commit: 6dd536d) (details / githubweb)
6. Remove vestiges of 32-bit support (commit: 30ab9bb) (details / githubweb)
7. Use allocatable register (ft0) as scratch register for single precision store (commit: 0bd2064) (details / githubweb)
8. Use '$' to escape asm symbols (commit: 8417d6f) (details / githubweb)
9. Remove vestiges of 32-bit support (commit: 35e85da) (details / githubweb)
10. riscv.S: use hex literal (commit: b63979a) (details / githubweb)
11. Group pattern matching cases together (commit: ce63bf4) (details / githubweb)
12. Use jr instead of jalr (commit: 72ce86b) (details / githubweb)
13. Changes (commit: ef7d00b) (details / githubweb)
14. check-typo (commit: 8ccd05d) (details / githubweb)
15. Allow t0 to be used for the register allocator (commit: ce361b9) (details / githubweb)
16. check-typo (commit: 54ddb27) (details / githubweb)