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Summary

  1. nvml: use the current PCI link speed (details)
  2. nvml: fix the PCI link speed for PCI Gen4+ (details)
  3. pci+nvml: factorize PCI link speed computation (details)
  4. rename.h: update with hwloc__pci_link_speed() (details)
Commit 42fea7bf6f65cea552a31bb7092432ff2320419d by brice.goglin
nvml: use the current PCI link speed

Not the max supported by the device, since it may be in a slower/narrower slot.

Just like we do in the PCI backend.

Signed-off-by: Brice Goglin <Brice.Goglin@inria.fr>
The file was modifiedconfig/hwloc.m4 (diff)
The file was modifiedhwloc/topology-nvml.c (diff)
The file was modifiedtests/hwloc/ports/include/nvml/nvml.h (diff)
Commit ca9f08973e11e7f71b6d10dbc6a4f30a4f5f9a4f by brice.goglin
nvml: fix the PCI link speed for PCI Gen4+

The code was never updated Gen>3.
We ignore slight encoding changes in last PCIe revisions,
but we'll factorize with the common PCI code soon anyway.

Thanks to Akram Sbaih for the report.

Closes #653

Signed-off-by: Brice Goglin <Brice.Goglin@inria.fr>
The file was modifiedhwloc/topology-nvml.c (diff)
Commit cc260153fc2da93828e02d9b67efbce17d7d4621 by brice.goglin
pci+nvml: factorize PCI link speed computation

So that we don't forget to update NVML when adding new PCI
revisions to the duplicated PCI code.
Also the new NVML code doesn't handle encoding changes
in last PCIe revisions.

Refs #653

Signed-off-by: Brice Goglin <Brice.Goglin@inria.fr>
The file was modifiedinclude/private/misc.h (diff)
The file was modifiedhwloc/pci-common.c (diff)
The file was modifiedhwloc/topology-nvml.c (diff)
Commit c6058d33e2fddf4229989ac363a154c5afb2346c by brice.goglin
rename.h: update with hwloc__pci_link_speed()

Forgotten in cc260153fc2da93828e02d9b67efbce17d7d4621

Signed-off-by: Brice Goglin <Brice.Goglin@inria.fr>
The file was modifiedinclude/hwloc/rename.h (diff)